1. Field of the Invention
This invention relates generally to a maintenance system and interface for use in a high-speed data processing system; and, more specifically, relates to a maintenance system for use in a modularized data processing system wherein maintenance operations must be completed in real time in each of the logical modules of the system substantially simultaneously and with minimum delay, and wherein the interface is implemented using a minimum number of pin resources.
2. Description of the Prior Art
As today's data processing systems increase in complexity, an ever-increasing number of maintenance functions are being added to provide debug, run-time analysis, and clock control capabilities. These functions are primarily used to accomplish debug and system analysis operations, but may also be used to accomplish system tasks such as clock synchronization. For example, trace capabilities may be added to the logic so that after the occurrence of an error, system analysis may be performed to determine the source of the error. These trace capabilities generally involve the addition of storage devices such as history stacks to a logic design. The history stacks capture the logic levels of critical ones of the signals at predetermined time intervals to create a trace of the events leading up to the error. The co-pending application entitled "Programmable Error Detect/Mask Utilizing Bus History Stack", Ser. No. 08/790,629 filed Jan. 29, 1997, and which is assigned to the assignee of the current invention, describes the use of history stacks in more detail.
Another example of maintenance functionality that may be added to aid in debug efforts includes clock control circuitry. This circuitry may be used to stop the clocks in one or more units of a data processing system following the occurrence of a predetermined error. This "slam-stop" capability allows the state of the system to be preserved and later analyzed so that the source of the error can be discovered. Similarly, it may be desirable to stop the clock in one or more units just prior to the occurrence of a known, re-creatable error. Single clock pulses may be provided to the logic so that the state of the logic prior to, and during the error, may be analyzed.
Some maintenance functions are used during normal system operations. For example, performance monitoring logic may be added to a system to capture data indicative of system throughput and loading. This type of logic might include counter circuits which record the number of requests made to particular units within a system. The captured performance data allows system analysts to determine how to obtain maximum efficiency from the system.
Another type of maintenance function required within the system involves clock synchronization. Often, more than one of the units within a system have a dayclock counter used to provide timestamp and scheduling information to the operating system or other application programs. These dayclock counters must be incremented in a synchronized manner. Logic is needed in the system to perform this synchronized clock operation.
The type of maintenance functions discussed above generally requires that one or more actions be taken within selected units of the system substantially simultaneously. For example, to provide data which accurately reflects system usage characteristics, the performance monitoring logic circuits within all units of a system should be enabled and disabled at the same time. Similarly, clock control operations must be performed in unison throughout the various units of a system. Likewise, history stack operations must be enabled or disabled throughout the system at approximately the same time so an accurate snapshot of system operations can be obtained. Moreover, it is important that various ones of the debug functions such as clock slam-stop operations be performed relatively quickly after an error occurs so that the state of the system at the time of the error is preserved.
Many prior art data processing systems provide dedicated logic for each of the maintenance functions included in the system. That is, individual logic is provided for controlling clock advance operations, different logic is provided for initiating slam-stop operations, and so on. Since dedicated logic interconnections are provided between the various units of the system for each maintenance function, the systems are logic intensive and utilize a large number of interconnecting pins. U.S. Pat. No. 5,040,108 to Kanazawa describes a system for stopping clock operations to predetermined error-collection registers within a processing unit following the occurrence of errors. Dedicated point-to-point lines communicate the occurrence of errors within one of the processing units to a central control processor. The control processor responds by issuing an instruction to the failing unit on dedicated interface lines, and the failing processing unit thereafter asserts a signal to stop the clocking of the error-collection registers. This system has the disadvantage of requiring separate error notification and response lines for each unit. In designs in which pin limitations are a consideration, the dedication of this number of pins to a single maintenance function is undesirable. Moreover, the use of an intervening control processor is undesirable in today's high-speed systems because the added delay required for the control processor to respond does not allow for substantially immediate action following the occurrence of an event. This may result in the loss of the state of the machine at the time the error occurred.
Another maintenance system and interface is disclosed in U.S. Pat. No. 5,581,482 to Wiedenman et al. assigned to the assignee of the current invention. The disclosed system describes dedicated hardware and interconnections which intercouple the various units of a data processor to accomplish performance monitoring and clock control functions. Because the maintenance functions are performed on separate dedicated interfaces, the system is not suitable for designs that are severely pin-limited.
One method of reducing the number of pin resources utilized within a maintenance system is to combine various logic event occurrences using a hierarchical logic tree structure so that fewer interconnecting nets are needed to transfer the event notifications to other units. U.S. Pat. No. 4,996,688 to Byers et al., which is assigned to the assignee of the current invention, discloses this type of a hierarchical structure. Multiple ranks of state devices are used to capture and combine logical events into an interrupt signal which is provided to a programmed micro-controller. Although this system is useful in consolidating the events so that fewer interconnecting resources are utilized, the multiple register ranks insert delay into the notification process.
What is needed is a general-purpose maintenance system and interface that utilizes a minimum number of pin resources, and whereby pre-selected ones of the units within a data processing system can be monitored for the occurrence of certain logical events. Upon the occurrence of one of the monitored events, a notification is provided substantially simultaneously to all units in the system so that a selected action or actions may be taken within selected ones of the units with minimal delay.